PIC16LF84A-04I/SS【PDF 52/80 页】IC MCU FLASH 1KX14 EE 20SSOP

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Sheet目录3833

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Micrel, Inc.

KSZ8851SNL/SNLI

August 2009

M9999-083109-2.0

Bit

Default Value

R/W

Description

0x0

RXMPDIE Receive Magic Packet Detect Interrupt Enable

When this bit is set, the Receive magic packet detect interrupt is enabled.

When this bit is reset, the Receive magic packet detect interrupt is disabled.

0x0

LDIE Linkup Detect Interrupt Enable

When this bit is set, the wake-up from linkup detect interrupt is enabled.

When this bit is reset, the linkup detect interrupt is disabled.

0x0

EDIE Energy Detect Interrupt Enable

When this bit is set, the wake-up from energy detect interrupt is enabled.

When this bit is reset, the energy detect interrupt is disabled.

0x0

SPIBEIE SPI Bus Error Interrupt Enable

When this bit is set, the SPI bus error interrupt is enabled.

When this bit is reset, the SPI bus error interrupt is disabled.

0x0

DEDIE Delay Energy Detect Interrupt Enable

When this bit is set, the delay energy detect interrupt is enabled.

When this bit is reset, the delay energy detect interrupt is disabled.

Note: the delay energy detect interrupt till device is ready for host access.

Interrupt Status Register (0x92 – 0x93): ISR

This register contains the status bits for all QMU and other interrupt sources.

When the corresponding enable bit is set, it causes the interrupt pin to be asserted.

This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register

bits are not cleared when read. The user has to write “1” to clear.

Bit

Default Value

R/W

Description

0x0

(W1C)

LCIS Link Change Interrupt Status

When this bit is set, it indicates that the link status has changed from link up to link down,

or link down to link up.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x0

(W1C)

TXIS Transmit Interrupt Status

When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the

MAC interface and the QMU TXQ is ready for new frames from the host.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x0

(W1C)

RXIS Receive Interrupt Status

When this bit is set, it indicates that the QMU RXQ has received at least a frame from the

MAC interface and the frame is ready for the host CPU to process.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x0

Reserved

0x0

(W1C)

RXOIS Receive Overrun Interrupt Status

When this bit is set, it indicates that the Receive Overrun status has occurred.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x0

Reserved

0x1

(W1C)

TXPSIS Transmit Process Stopped Interrupt Status

When this bit is set, it indicates that the Transmit Process has stopped.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x1

(W1C)

RXPSIS Receive Process Stopped Interrupt Status

When this bit is set, it indicates that the Receive Process has stopped.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

0x0

Reserved

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